Precharge Voltage Supplying Circuit

ABSTRACT

A precharge voltage supplying circuit comprises a transistor operating in response to a control signal, wherein the transistor is connected between a first node to which an internal voltage is supplied and a second node to which a precharge voltage is supplied, and a resistance element connected in parallel to the transistor between the first node and the second node.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No. 12/005,706filed Dec. 28, 2007, claiming priority to Korean application numbers10-2007-0026584 and 10-2007-0063927, filed on Mar. 19, 2007, and Jun.27, 2007, respectively, the entire contents of each of which areincorporated herein by reference.

BACKGROUND

Recently, the capacity of semiconductor memory devices is rapidlybecoming larger and studies on methods to increase an operational speedand reduce current consumption are steadily conducted. Particularly,techniques to reduce the current consumption are developed in asemiconductor memory device which can be embedded in a portable systemsuch as a cellular phone or a notebook computer.

One of the above mentioned techniques is to minimize the currentconsumption in a core area of a memory. The core area having a pluralityof memory cells, bit lines and word lines is designed according to acritical design rule. Thus, the memory cells can be very small andoperate with a low power consumption.

Particularly, a bit line precharge technique is important to increasethe speed of a cell data access. The bit line precharge techniqueprecharges a bit line (BL) to a half level of a core voltage (VCORE)before the data access in order to increase the speed of the dataaccess.

Meanwhile, in a standby state, a potential difference occurs between aword line (WL) of 0V and a precharged bit line (BL). If a bridge occursbetween the word line (WL) and the bit line (BL), a current consumptionincreases due to the bridge current which is caused by the potentialdifference. Therefore, in order to reduce the current consumption causedby the bridge current, a precharge voltage supplying circuit, which hasa bleeder resistance, is used to generate a precharge voltage (VBLP) onthe bit line where a voltage drop occurs.

SUMMARY

In an exemplary embodiment, a precharge voltage supplying circuitcomprises a transistor operating in response to a control signal,wherein the transistor is connected between a first node to which aninternal voltage is supplied and a second node to which a prechargevoltage is supplied; and a resistance element connected in parallel tothe transistor between the first node and the second node.

In another exemplary embodiment, a precharge'voltage supplying circuitcomprises a transistor operating in response to a control signal,wherein the transistor is connected between a first node to which aninternal voltage is supplied and a second node to which a prechargevoltage is supplied; and a resistance element connected in series to thetransistor between the first node and the second node.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features and other advantages will be moreclearly understood from the following detailed description taken inconjunction with the accompanying drawings, in which:

FIG. 1 is a circuit diagram of a precharge voltage supplying circuitaccording to an embodiment of the present disclosure.

FIGS. 2A and 2B are graphs illustrating a precharge voltagecharacteristic and a bridge current characteristic, respectively, in thecircuit of FIG. 1.

FIG. 3 is a circuit diagram of a precharge voltage supplying circuitaccording to another embodiment of the present disclosure.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, embodiments of the present invention will be described withreference to accompanying drawings. However, the embodiments are forillustrative purposes only and are not intended to limit the scope ofthe invention.

FIG. 1 is a circuit diagram of a precharge voltage supplying circuitaccording to an embodiment of the present disclosure.

Referring to FIG. 1, the precharge voltage supplying circuit includes afirst switch unit 31, a bleeder resistance unit 32 and a second switchunit 34 which connects node C to node D.

The first switch unit 31 includes a logic unit 300 and an NMOStransistor N30 which is connected between node C and node D and isturned on in response to an output signal of the logic unit 300. Thelogic unit 300 includes a NOR gate NR30 receiving a test mode signalTM_BLEEDER_PWDD and a ground voltage VSS to perform a NOR operation, andinverters IV30 and IV31. Here, it is desirable to design the NMOStransistor N30 to have a large size.

The bleeder resistance unit 32 includes an NMOS transistor N31 which isconnected between node C to which the internal voltage Vp is suppliedand node D to which the precharge voltage VBLP is supplied and operatesin response to the control signal BLEEDER_S, and a resistance elementR30 which is in parallel connected to the NMOS transistor N31 betweennode C and node D.

Operation of the precharge voltage supplying circuit of FIG. 1 will bedescribed below in detail.

The bleeder resistance unit 32 operates in accordance with the test modesignal TM_BLEEDER_PWDD. First, in a case that the test mode signalTM_BLEEDER_PWDD is in a low level, the output signal of the logic unit300 is in a high level and the NMOS transistor N30 is turned on. Sincethe size of the NMOS transistor N30 is large, the voltage drop betweennode C and node D through the turn-on resistance of the NMOS transistorN30 is not so large. Thus, the precharge voltage VBLP, having a levelwhich is almost the same as the internal voltage Vp, is output to nodeD. At this time, there is almost no voltage drop through the bleederresistance unit 32 which includes the NMOS transistor N31 and theresistance element R30. Also, if the second switch unit 34 is turned onso that node C is connected to node D, operations of the NMOS transistorN31 and the bleeder resistance unit 32 are bypassed, and the prechargevoltage VBLP, having a level which is almost the same as the internalvoltage Vp, is output through node D.

Meanwhile, in a case that the test mode signal TM_BLEEDER_PWDD is in ahigh level, the output signal of the logic unit 300 is in a low leveland the NMOS transistor N30 is turned off. Thus, a voltage drop of theinternal voltage Vp occurs through the bleeder resistance unit 32 sothat a voltage-dropped signal is output as the precharge voltage VBLPthrough node D. At this time, since the bleeder resistance unit 32includes the NMOS transistor N31 and the resistance element R30, thesecond bit line precharge voltage VBLP is adjustable in various levelsaccording to a PVT fluctuation and the range in the fluctuation is notso large. This is due to the characteristic of the NMOS transistor N31,which has various turn-on resistance values according to the PVTfluctuation, and the characteristic of the resistance element R30, whichhas a constant resistance value regardless of the PVT characteristicchange.

Referring to FIG. 2A, although the precharge voltage VBLP, correspondingto a bridge resistance Rbr, has various levels according to the PVTfluctuation, the range in the fluctuation is not so large. As shown inFIG. 2B, the level of the precharge voltage VBLP is highest when the PVTfluctuation is “FFFH”, and the level of the precharge voltage VBLP islowest when the PVT fluctuation is “SSSH”. Here, “SSFR”, “FFFR”, “FFFO”,“FFFH”, “FFSH” and “SSSH” show the PVT fluctuation respectively. Forexample, “SSSH” means that a process speed of an NMOS transistor and aPMOS transistor is slow, a voltage is low, and a temperature is hot.Also, referring to FIG. 2B, although a bridge current Ibr has variouslevels according to the PVT fluctuation, the range in the fluctuation isnot so large. Here, the bridge resistance Rbr is a sampling resistorhaving the same resistance with a region where the bridge current Ibr isgenerated when a bridge occurs between the word line (WL) and the bitline (BL).

FIG. 3 is a circuit diagram of a precharge voltage supplying circuitaccording to another embodiment of the present disclosure.

Referring to FIG. 3, the precharge voltage supplying circuit includes afirst switch unit 50, a bleeder resistance unit 52 and a second switchunit 54 which connects node E to node F.

The first switch unit 50 includes an NMOS transistor N50 and a PMOStransistor P50 which are connected between node E and node F and areturned on in response to enable signals BLEEDER OFF and BLEEDER OFFB.Here, it is desirable to design the NMOS transistor N50 and the PMOStransistor P50 to have a large size.

The bleeder resistance unit 52 includes NMOS transistors N51 to N54which are connected between node E to which the internal voltage Vp isapplied and node F to which the precharge voltage VBLP is supplied andoperate in response to the control signals BLEEDER_XL, BLEEDER_L,BLEEDER_M and BLEEDER_S, respectively, and resistance elements 10K, 20K,40K and 80K which are in series connected with the NMOS transistors N51to N54, respectively.

Operation of the precharge voltage supplying circuit of FIG. 3 will bedescribed below in detail.

The bleeder resistance unit 52 operates in response to the enablesignals BLEEDER OFF and BLEEDER OFFB. First, in a case that the enablesignals BLEEDER OFF and BLEEDER OFFB are in high and low levels,respectively, the NMOS transistor N50 and the PMOS transistor P50 areturned on. Since the sizes of the NMOS transistor N50 and the PMOStransistor P50 are large, the voltage drop between node E and node Fthrough the turn-on resistance of the NMOS transistor N50 and the PMOStransistor P50 is not so large. Thus, the second bit line prechargevoltage VBLP, having a level which is almost the same as the internalvoltage Vp, is output through node F. At this time, there is almost novoltage drop through the bleeder resistance unit 52 which includes theNMOS transistors N51 to N54 and the resistance elements 10K, 20K, 40Kand 80K. Also, if the second switch unit 54 is turned on so that node Eis connected to node F, operation of the bleeder resistance unit 52 isbypassed, and the second bit line precharge voltage VBLP, having a levelwhich is almost the same as the internal voltage Vp, is output throughnode F.

Meanwhile, in a case that the enable signal BLEEDER OFF is in a lowlevel, the NMOS transistor N50 and the PMOS transistor P50 are turnedoff. Thus, a voltage drop of the internal voltage Vp occurs through thebleeder resistance unit 52 so that the voltage-dropped signal isoutputted as the precharge voltage VBLP through node F. At this time,since the bleeder resistance unit 52 includes the NMOS transistors N51to N54 and the resistance elements 10K, 20K, 40K and 80K, the prechargevoltage VBLP is adjustable in various levels according to a PVTfluctuation and the range in the fluctuation is not so large. At thistime, the level of the precharge voltage VBLP is adjustable according tothe control signals BLEEDER_XL, BLEEDER_L, BLEEDER_M and BLEEDER_S. Forexample, in a case that the control signals BLEEDER_L, BLEEDER_M andBLEEDER_S are in a low level and only the control signal BLEEDER_XL isin a high level, the part which outputs the precharge voltage VBLPthrough node F with the voltage drop of the internal voltage Vp becomesthe NMOS transistor N54 which is turned on and the resistance element80K. It is possible to generate the precharge voltage which has variousvoltage levels based on the selective activation of the control signalsBLEEDER_XL, BLEEDER_L, BLEEDER_M and BLEEDER_S.

Although various examples and exemplary embodiments of a prechargevoltage supplying circuit that can be used to generate a bit lineprecharge voltage for performing a bit line precharge operation aredescribed in the present disclosure, it can also be widely used invarious other devices which need generation of a voltage, a level ofwhich is adjustable according to a PVT characteristic change, and arange in change of which is not so large.

Although examples and exemplary embodiments of the invention have beendisclosed for illustrative purposes, those skilled in the art willappreciate that various modifications, additions and substitutions arepossible, without departing from the scope and spirit of the disclosureand the accompanying claims. For example, elements and/or features ofdifferent examples and illustrative embodiments may be combined witheach other and/or substituted for each other within the scope of thisdisclosure and appended claims.

1-19. (canceled)
 20. A precharge voltage supplying circuit, comprising:a transistor operating in response to a control signal, wherein thetransistor is connected between a first node to which an internalvoltage is supplied and a second node to which a precharge voltage issupplied; and a resistance element connected in parallel to thetransistor between the first node and the second node.
 21. The prechargevoltage supplying circuit of claim 20, wherein the precharge voltage issupplied to a pair of bit lines in response to a bit line equalizingcontrol signal.
 22. The precharge voltage supplying circuit of claim 20,wherein the precharge voltage is produced by a voltage drop across theresistance element or by a voltage drop across the transistor which isturned on in response to the control signal.
 23. A precharge voltagesupplying circuit, comprising: a transistor operating in response to acontrol signal, wherein the transistor is connected between a first nodeto which an internal voltage is supplied and a second node to which aprecharge voltage is supplied; and a resistance element connected inseries to the transistor between the first node and the second node. 24.The precharge voltage supplying circuit of claim 23, wherein theprecharge voltage is supplied to a pair of bit lines in response to abit line equalizing control signal.
 25. The precharge voltage supplyingcircuit of claim 26, further comprising: wherein the logic unit includesa NOR gate for a NOR operation of a ground voltage signal and the testmode signal.
 26. The precharge voltage supplying circuit of claim 23,further comprising: a logic unit configured to receive a test modesignal and produce an enable signal; and a switching element forconnecting the first and second nodes in response to the enable signalfrom the logic unit.
 27. The precharge voltage supplying circuit ofclaim 23, wherein the switching element is a NMOS transistor connectedbetween the first node and the second node.
 28. The precharge voltagesupplying circuit of claim 20, further comprising: a logic unitconfigured to receive a test mode signal and produce an enable signal;and a switching element for connecting the first and second nodes inresponse to the enable signal from the logic unit.
 29. The prechargevoltage supplying circuit of claim 28, wherein the logic unit includes aNOR gate for a NOR operation of a ground voltage signal and the testmode signal.
 30. The precharge voltage supplying circuit of claim 29,wherein the switching element is a NMOS transistor connected between thefirst node and the second node.